There has been an increasing demand for electrically erasable and programmable memory devices that do not require refreshing of data stored therein. Current trends of memory devices have been to increase capacity and reliability. A NAND-type flash memory is an example of a non-volatile semiconductor memory device that provides relatively large capacity and relatively high reliability without refreshing stored data. Because data can be maintained without power, flash memory devices have been widely applied to battery powered electronic devices (e.g., hand-held terminals and computers, etc.) where power may be interrupted suddenly.
A NAND-type flash memory may include electrically erasable and programmable read-only memory cells called “flash EEPROM cells”. Commonly, a flash EEPROM cell may include a memory cell transistor or a floating gate transistor, which may be formed on a pocket P-well region of a substrate and may have spaced apart N-type source and drain regions, a floating gate formed over a channel region between the source and drain regions to store charge, and a control gate placed over the floating gate.
A NAND-type flash memory may include a memory cell array, having a plurality of strings (called cell strings or NAND strings) corresponding to bit lines, respectively. Each cell string may include a string select transistor as a first select transistor, a ground select transistor as a second select transistor, and plural memory cells connected in series between the string and ground select transistors. A string select transistor in each string may have a drain connected to a corresponding bit line and a gate connected to a string select line. Aground select transistor in each string may have a source connected to a common select line and a gate connected to a ground select line. Memory cells in each string may be connected in series between a source of the string select transistor and a drain of the ground select transistor. Memory cells in each string may be connected to corresponding word lines, respectively.
Initially, for example, memory cells can be erased to have a threshold voltage of −3V. A threshold voltage of a selected memory cell may be shifted to a higher voltage range by applying a relatively high voltage (or a program voltage) (e.g., 20V) to a word line of the selected memory cell at a predetermined time. Threshold voltages of remaining or unselected memory cells are not significantly varied.
One problem may arise when programming a portion of memory cells (hereinafter, referred to as “program memory cells”) in a selected word line and program-inhibiting remaining memory cells (hereinafter, referred to as “program-inhibit memory cells”) in the selected word line. When a program voltage is applied to a selected word line, it may be applied to program memory cells and to program-inhibit memory cells at the same time. Program-inhibit memory cells in the selected word line may be programmed according to a phenomenon referred to as “program disturbance”.
One method for reducing the program disturbance is a program inhibition method using a self-boosting scheme. Program inhibition methods using self-boosting schemes are discussed, for example, in U.S. Pat. No. 5,677,873 entitled “METHODS OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PREVENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN” and in U.S. Pat. No. 5,991,202 entitled “METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY”. The disclosures of both of these patents are herein incorporated by reference.
A program inhibition method using such a self-boosting scheme will be described below with reference to FIG. 1. A ground path may be formed by applying a voltage of 0V to a gate of a ground select transistor GST. A voltage of 0V may be applied to a selected bit line (e.g., BL0) and a power supply voltage Vcc(as a program inhibition voltage) may be applied to an unselected bit line (e.g., BL1). Simultaneously, a power supply voltage Vcc may be applied to a string select line SSL. A source of a string select transistor SST connected to the unselected bit line BL1 may be charged up to Vcc−Vth (Vth being a threshold voltage of the string select transistor), and then the transistor SST connected to the unselected bit line BL1 ay be shut off. A program voltage Vpgm can be applied to a selected word line (e.g., WL14) and a pass voltage Vpass can be applied to unselected word lines (e.g., WL0–WL13, WL15), and a channel voltage of a program-inhibit cell transistor can be boosted by the program voltage Vpgm. The boosted channel voltage may be expressed by the following equation:       V    ch    =                              V          cc                -                  V          th                    N        +                  V        pgm            ⁢                                    C            i                                              C              t                        +                          C              ch                                      .            In this equation, N is a word line number, Vth is a threshold voltage of a string select transistor, Cch is a channel capacitance of a program-inhibit cell transistor, and Ct is a total capacitance of the program-inhibit cell transistor. The Ct is (Cono∥∥Ctun) wherein Cono and Ctun are coupling capacitances.
Although a program voltage is applied to a control gate of a program-inhibit cell transistor, a boosted channel voltage may reduce F-N tunneling between a floating gate and a channel of the program-inhibit cell transistor. Accordingly, the program-inhibit cell transistor may maintain an initial erased state.
Another program-inhibit method using a local self-boosting scheme is discussed, for example, in U.S. Pat. No. 5,715,194 entitled “BIAS SCHEME OF PROGRAM INHIBIT FOR RANDOM PROGRAMMING IN A NAND FLASH MEMORY” and in U.S. Pat. No. 6,061,270 entitled “METHOD FOR PROGRAMMING A NON-VOLATILE MEMORY DEVICE WITH PROGRAM DISTURB CONTROL”. The disclosures of both of these patents are herein incorporated by reference.
A program inhibition method using such a local self-boosting scheme will be described below with reference to FIG. 2. A voltage of 0V can be applied to a selected bit line (e.g., BL0), and a power supply voltage Vcc (as a program inhibition voltage) can be applied to an unselected bit line (e.g., BL1). Since a power supply voltage is applied to a string select line SSL, a source of a string select transistor SST connected to the unselected bit line BL1 may be charged up to Vcc−Vth (where Vth is a threshold voltage of the string select transistor). The transistor SST connected to the unselected bit line BL1 can than be shut off.
A decoupling voltage Vdcp of 0V can be applied to unselected word lines (e.g., WL13 and WL15) closely adjacent to a selected word line (e.g., WL14). A pass voltage Vpass (e.g., 10V) can be applied to remaining word lines (e.g., WL0–WL12). The selected word line can then be supplied with a program voltage Vpgm. With this bias condition, since a channel of a program-inhibit cell transistor may be limited by cell transistors of unselected word lines supplied with a decoupling voltage, a boosted channel voltage of the program-inhibit cell transistor can be higher than that caused by the above self-boosting scheme. Similar to the self-boosting method, the boosted channel voltage may reduce F-N tunneling between a floating gate and a channel of a program-inhibit cell transistor so that the program-inhibit cell transistor can maintain an initial erase state.
Methods using the local self-boosting scheme may obtain a higher channel voltage than the self-boosting scheme and may thus be used to program a multi-level cell that stores n-bits of data (where n is an integer greater than or equal to 2). However, the local self-boosting scheme may have a lower program speed as compared with the self-boosting scheme.
In general, a voltage of a floating gate of a memory cell transistor to be programmed may be affected by voltages of floating gates of adjacent cell transistors through capacitive coupling. Such a phenomenon is discussed, for example, in the IEEE ELECTRON DEVICE LETTERS, VOL.23, NO.5, pp. 264 to 266, May 2002 under the title of “EFFECTS OF FLOATING-GATE INTERFERENCE ON NAND FLASH MEMORY CELL OPERATION.” The disclosure of this reference is incorporated herein by reference. At any memory cell transistor (hereinafter called “reference memory cell transistor”), as shown in FIG. 3, coupling capacitances Cono, Cfg and Ctun may exist between a floating gate and a channel (bulk or body) of the reference memory cell transistor and between the floating gate of the reference memory cell transistor and floating gates of adjacent memory cell transistors, respectively. A voltage of a floating gate of the reference memory cell transistor may be affected by the coupling capacitances.
A coupling ratio to a control gate of the reference memory cell transistor may be expressed as follows:       γ    ono    =                    C        ono                              C          tun                +                  C          ono                +                  2          ⁢                      C            fg                                .  In this equation, Cono is a control gate-to-floating gate capacitance, Ctun is a floating gate-to-channel capacitance, and Cfg is a floating gate-to-floating gate capacitance.
A voltage V1 of a floating gate of a memory cell transistor connected to a first unselected word line may be expressed as follows:   V1  =                    γ        ono            ⁢              V        cg1              =                                        C            ono                    ⁢                      V                          cg              ⁢                                                          ⁢              1                                                            C            tun                    +                      C            ono                    +                      2            ⁢                          C              fg                                          .      In this equation, Vcg1 is a voltage applied to a control gate, that is, a voltage applied to an unselected word line.
A voltage V2 of a floating gate of a memory cell transistor connected to a second unselected word line may be expressed as follows:   V2  =                    γ        ono            ⁢              V        cg2              =                                        C            ono                    ⁢                      V                          cg              ⁢                                                          ⁢              2                                                            C            tun                    +                      C            ono                    +                      2            ⁢                          C              fg                                          .      In this equation, Vcg2 is a voltage applied to a control gate, that is, a voltage applied to an unselected word line.
Accordingly a voltage Vfg of a floating gate of a reference memory cell transistor may be determined as follows:Vfg=γONOVcg+γONOγfgVcg1+γONOγfgVcg2.
With the local self-boosting method, a program voltage Vpgm may be applied to a selected word line (e.g., WL14), while a decoupling voltage Vdcp may be applied to two unselected word lines WL13 and WL15 closely adjacent to the selected word line WL14. Based on this bias condition, a voltage of a floating gate of the reference memory cell transistor may be expressed as follows:Vfg=γONOVpgm(WL14)+γONOγfgVdcp(WL13) +γONOγONOγfgVdcp(WL15).
Since word lines WL13 and WL15 adjacent to a selected word line WL14 are supplied with 0V, values of γONOγfgVdcp(WL13) and γONOγfgVdcp(WL15) become 0V. Therefore, the floating gate voltage Vfg of the reference memory cell transistor may become a voltage of γONOγfgVdcp(WL13).
In accordance with the above description, since a floating gate voltage Vfg of a reference memory cell transistor may be unaffected by voltages V1 and V2 of floating gates placed at both sides of the floating gate of a reference memory cell transistor, a program speed of a local self-boosting method may be slower than that of a self-boosting method. That is, in the case of the self-boosting method where a pass voltage is applied to unselected word lines, a floating gate voltage of a reference voltage may be increased by capacitive coupling, so that a program speed is increased as compared with the local self-boosting method.
In case of a NAND flash memory which performs a program operation using an “incremental step pulse programming (ISPP) scheme”, a program voltage Vpgm, for example, can be stepwise increased from 14.7V to 20V as a program cycle is repeated. If a program speed is reduced, a number of program cycles may increase. When using an ISSP scheme, an increase in the program cycle number may require a higher program voltage. This may increase a peripheral circuit (in particular, a high voltage pump) area and a program time. Increases in the peripheral circuit area may result in an increase in a number of high voltage pumping stages used to generate higher voltages.